1. Field Of The Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for providing very fast modes of operation in a frame buffer which stores data for display on an output display device.
2. History Of The Prior Art
One of the significant problems involved in increasing the operational speed of desktop computers has been in finding ways to increase the rate at which information is transferred to an output display device. Many of the various forms of data presentation which are presently available require that copious amounts of data be transferred. For example, if a computer output display monitor is operating in a color mode in which 1024.times.780 pixels are displayed on the screen and the mode is one in which thirty-two bits are used to define each pixel, then a total of over twenty-five millions bits of information must be transferred to the screen with each frame that is displayed. Typically, sixty frames are displayed each second so that over one and one-half billion bits must be transferred each second in such a system. This requires a very substantial amount of processing power. In general, the transfer of this data to the display slows the overall operation of the computer.
In order to speed the process of transferring data to the display, various accelerating circuits have been devised. In general, these circuits are adapted to relieve the central processor of the computer of the need to accomplish many of the functions necessary to transfer data to the display. Essentially, these accelerating circuits take over various operations which the central processor would normally be required to accomplish. For example, block transfers of data from one position on the screen to another require that each row of pixel data on the screen being transferred be read and rewritten to a new row. Storing information within window areas of a display requires that the data available for each window portion be clipped to fit within that window portion and not overwrite other portions of the display. Many other functions require the generation of various vectors each time an image within a window on the display is moved or otherwise manipulated. When accomplished by a central processing unit, all of these operations require a substantial portion of the operational time of the central processing unit. Many of these repetitive functions may be accomplished by a graphics accelerator so that the central processor is relieved of this burden. In general, it has been found that if operations which handle a great number of pixels at once are mechanized by a graphics accelerator, then the greatest increase in display speed may be attained. This, of course, speeds the operations involved in the display of graphical material.
A problem which has been discovered by designers of graphics accelerator circuitry is that a great deal of the speed improvement which is accomplished by the graphics accelerator circuitry is negated by the frame buffer circuitry into which the output of the graphics accelerator is loaded for ultimate display on an output display device. Typically a frame buffer offers a sufficient amount of dynamic random access memory (DRAM) to store one frame of data to be displayed. However, transferring the data to and from the frame buffer is very slow because of the manner in which the frame buffers are constructed. Various improvements have been made to speed the access to frame buffers. For example, two-ported video random access memory (VRAM) has been substituted for dynamic random access memory so that information may be taken from the frame buffer at the same time other information is being loaded.
A block mode of writing has been devised for certain frame buffers which handle four bit color modes in order to increase writing speed. In this block mode, the data transferred on the data bus indicates, not pixel values, but control signals signifying whether a pixel is to be written or not. A color register stores a color value which is written to the pixel position of the pixel position is enabled by the control signal on the data bus. Nothing is written to a pixel position which is not enabled. This block mode of operation allows simultaneous writes of the single color stored in the color register to a number of pixel positions equal to the number of conductors on the data bus.
Using this block mode of operation with a color value register speeds up writing four bit color to a frame buffer under many of the conditions in which lack of speed is most obvious. Unfortunately, this mode of operation has a number of limitations. First, it has been used only with systems using four bit color pixels and has never been adapted to use with more modern color systems. More importantly, typical operations which are accomplished with the data in any window of the display involve a manipulation of two colors. For example, when text is written to the screen, the color of each letter and the color of the background surrounding that letter are manipulated by varying the pixels stored in the frame buffer for describing the image on the display. Unless both colors are written, no outline is provided for the text. Both the software which provides data for display and the various graphical rendering devices which accelerate the manipulation of that data are capable of manipulating two colors at once and usually do so. However, the frame buffers which are available for desktop computers are capable of varying no more than a single color at a time in the block mode in which a number of pixels may be addressed simultaneously. Thus, though the modern rendering devices speed up the manipulation of data, the presentation slows at the frame buffer which is able to accept only a single color at a time when presented data in the block mode of operation. This problem has been especially acute because each time a different color is used for a group of pixels, the color register must be updated from the old color value to the new color value in a time consuming operation before the new color may be used. Thus, a background color must be first placed in the color value register in one operation for a first row on the display. Next, the pixels of that color must be written to various pixel positions in the frame buffer. Then, the color must be changed to the foreground color in the register, and those pixels of the foreground color described in a second write operation. When, the next row of pixels is written to the frame buffer, the entire operation must be repeated again.
Recently, an arrangement has been devised which allows two colors to be written simultaneously in a block mode write operation which may be used for more modern color modes. The arrangement uses a plurality of color value registers on the frame buffer to store a plurality of color values. This arrangement eliminates the necessity to reload the color value registers during the writing of a window, allows multiple color modes to be utilized, and accelerates writing dramatically. The arrangement is described in detail in co-pending U.S. patent application Ser. No. 08/145,756, entitled Apparatus For Providing Fast Multi-Color Storage In A Frame Buffer, Priem et al., filed on even date herewith, now U.S. Pat. No. 5,504,855.
One of the slowest operations performed using a prior art frame buffer is the scrolling of data. In a scrolling operation rows of data are moved up or down on the output display. Since the data describing the pixels which are displayed on an output display device is stored in a frame buffer, scrolling requires that the pixel data in the frame buffer describing a row of the display be read from the frame buffer by the central processor and then written back to another position in the frame buffer. In a typical personal computer, thirty-two bits of data (one pixel in thirty-two bit color or four pixels is eight bit color) are read from the frame buffer in an operation that typically requires 120 nanoseconds. This is followed by an access to write the data back to the appropriate positions in the frame buffer which again requires 120 nanoseconds. This pattern of reading and writing is continued until an entire row has been read and rewritten. Since a typical screen may hold rows of 1024 pixels, 240 nanoseconds times 1024 pixels is required to scroll a single row of thirty-two bit color pixels on the display or one-fourth that time for eight bit pixels. Each line of text takes up approximately twelve rows of pixels so scrolling a line of text takes a very long time.
The frame buffer described in the above-mentioned patent application may be modified to include new circuitry for providing very fast scrolling of data. Such scrolling is approximately 85 times faster than scrolling in prior art frame buffers. The arrangement is described in detail in co-pending U.S. patent application Ser. No. 08/145,791, entitled Method and Apparatus For Increasing The Rate Of Scrolling In A Frame Buffer Designed For Windowing Operations, Priem et al., filed on even date herewith.
Along with the new frame buffer described in the above-mentioned patent applications, new apparatus and methods of writing large blocks of data to a frame buffer have been devised which greatly accelerate writing to a frame buffer. The details of this apparatus and associated methods are described in co-pending U.S. patent application Ser. No. 08/145,755, entitled Multiple Block Mode Operations In A Frame Buffer System Designed For Windowing Operations, Priem et al., filed on even date herewith, now U.S. Pat. No. 5,533,187.
Even with these improvements, frame buffers still lack sufficient speed. One of the problems which all frame buffers have faced is that they have been designed so that a row address strobe cycle and a column address strobe cycle are necessary concomitants of almost all of the operations performed using the frame buffer. Naturally, when a memory cell in the random access memory in which the frame buffer stores its pixel data is accessed to read or write the pixel data, a row address strobe cycle and a column address strobe cycle are used for the access. However, in typical frame buffers such RAS and CAS cycles are also required when a frame buffer register is accessed, when pixel data is transferred in entire rows to the display, and for many other operations. Most of these operations have little or nothing to do with selecting a particular row or column in the frame buffer array yet row address and column address strobe cycles are still required. At the present state of the art, a typical row address strobe cycle requires 120 nanoseconds to accomplish while a typical column address strobe cycle requires 20 nanoseconds. The necessity of these strobe cycles, especially the row address strobe cycle, substantially lengthens the access time for these non-related functions.